1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of updating data stored in the semiconductor memory device, and, more particularly is suitably applied to a method of reducing deterioration in a data storage characteristic due to deviation of ON time of a P-channel field effect transistor included in a static random access memory (SRAM).
2. Description of the Related Art
It is known that the P-channel field effect transistor is deteriorated with time because of negative bias temperature instability (NBTI). The aged deterioration due to the NBTI is a phenomenon in which, when an ON state of the P-channel field effect transistor lasts for a long time under a high-temperature condition (e.g., when a source voltage and a drain voltage are 0 volt and a gate voltage is a negative bias), a threshold voltage of the P-channel field effect transistor rises and a current driving ability thereof falls.
When the aged deterioration due to the NBTI occurs only in one of a pair of P-channel field effect transistors included in a SRAM cell, in some case, the balance of a latch characteristic of the SRAM cell is broken and data stored in the SRAM cell is lost.
For example, Japanese Patent Application Laid-Open No. 2006-252696 discloses a method of enabling an electronic system realized by a field effect transistor (FET) to reduce a threshold voltage shift due to bias temperature instability (BTI) by guaranteeing that a specific storage element is in a first state in a period of a first section of time in which the electronic system operates and, in that period, data is stored in the storage element in a first phase and that the specific storage element is in a second state in a period of a second section in the time in which the electronic system operates and, in that period, data is stored in the storage device in a second phase.
However, in the method disclosed in Japanese Patent Application Laid-Open No. 2006-252696, when a memory cell array includes a large number of memory cells, if memory cells in which data is inverted and memory cells in which data is not inverted are mixed, the data stored in the respective memory cells cannot be accurately read out.